B.Tech tuitions in Delhi Lecture schedule 8th Jul 2015
Tejas Engineers Academy is a leading institute providing B.Tech tuitions in Delhi for all major subjects of engineering like Applied Mathematics, Applied Physics, and Engineering Mechanics. Following is the schedule of B.Tech tuitions in Delhi on Tejas Engineers Academy
| Time and Subject |
Topics |
Batch Details |
| 3pm to 5 pm
(Analog Electronics)
Category: B Tech Tuitions in Delhi for Analog Electronics |
Topics:- Small signal analysis of BJT, Analysis of BJT using hybrid model, Finding the current gain, voltage gain, overall voltage gain etc.
Category:- B.Tech tuitions in Delhi for Hybrid model, B. Tech tuitions in Delhi for BJT analysis using h-model. |
Prateek Batch |
| 5 pm to 7 pm
Subject: – Digital system design |
Latches, Types of latches, flip flops, SR flip flop, JK flip flop, Master slave JK flip flop, Race conditions, Excitation table of JK flip flop and applications.
Category:- B.Tech tuitions in Delhi for Flip flops, B.Tech tuitions in Delhi for JK flip flops and applications. |
Saksham Batch |
Explanation:- Hybrid model of BJT is an equivalent circuit of BJT in terms of four h parameters. These parameters are very important for analysis of BJT as an amplifier. Hybrid equivalent circuit of a given amplifier can be formed by first short circuiting all the supply voltages, short circuiting the capacitors and removing the BJT. We then replace the BJT with its equivalent h-model then apply all KVL and KCL laws to find current gain, voltage gain, overall current gain, overall voltage gain, input resistance, output resistance etc.
Latch is a circuit which is used to store one bit memory. Thus latch is also called one bit memory cell. An example of Latch circuit is SR latch. It can be formed by connecting two NOR gates, or two NAND gates with each other. A latch is also called bistable element. When we provide the provision of clock in a latch circuit then it becomes flip flop. Thus flip flop is a latch provided with a clock signal. Example of flip flops are SR, JK, D and T flip flops. Flip flops are characterized by their excitation tables. These are used to design sequential circuits like counters, registers state machines etc.
